The present invention relates to random-accessible semiconductor storage devices and, more particularly, to a nonvolatile semiconductor storage device including a ferroelectric thin-film capacitor.
In recent years, there have been researched and developed storage devices employing ferroelectric thin film in a storage-use capacitor (hereinafter, referred to as ferroelectric memory), some of which have been put into practical use. This type of ferroelectric memory has such features as nonvolatile random accessibility, high-speed write and read, and multi-time rewritability.
The storage device using ferroelectric thin film is currently available in the following first and second modes, roughly, as classified below. In the first place, the first mode is a destructive ferroelectric memory which uses a capacitor having a ferroelectric thin film sandwiched between upper and lower electrodes (hereinafter, referred to as ferroelectric capacitor) and which reads, by a sense amplifier, voltages of bit lines that occur depending on output charge amounts upon applying a voltage to this ferroelectric capacitor.
In this case, output charge amount differs between cases where the direction of spontaneous polarization of the ferroelectric capacitor is inverted by the applied voltage and where not inverted. The ferroelectric memory stores and reads data on the basis that polarization in the direction of this inversion or non-inversion is taken as data of xe2x80x9c1xe2x80x9d or xe2x80x9c0.xe2x80x9d
Two types are available for this ferroelectric memory as the first mode, i.e., 1T1C type ferroelectric memory which uses one ferroelectric capacitor and one selector transistor for one piece of information like DRAM (Dynamic Random Access Memory) and 2T2C type ferroelectric memory which uses two ferroelectric capacitors and two selector transistors for the same.
In the 1T1C type ferroelectric memory, a read voltage is applied to ferroelectric capacitors of selected memory cells for driving, and charges in amounts corresponding to data that have previously been written in the ferroelectric capacitors are outputted to bit lines for data read by a sense amplifier. For this operation, a reference voltage for comparison with the sense amplifier needs to be generated with a dummy cell (reference cell) or the like. It is noted that the reference voltage is required to fall between the voltages corresponding to xe2x80x9c1xe2x80x9d and xe2x80x9c0,xe2x80x9d desirably being just intermediate therebetween for the ensuring of margin.
Now basic properties of a semiconductor storage device using the 1T1C type ferroelectric memory are explained.
As a voltage is applied to between first and second electrodes of the ferroelectric capacitor, in which a ferroelectric thin film is sandwiched by the first and second electrodes, the amount of polarization of the ferroelectric capacitor draws a hysteresis loop as shown in FIG. 7. In FIG. 7, increasing a drive voltage VD from the state of a point A (drive voltage VD=0) causes the amount of polarization of the ferroelectric to increase nonlinearly as indicated by arrows so as to reach a point B (VD=maximum drive voltage VDMAX). Further, lowering the drive voltage VD back to 0 causes the amount of polarization to draw a curve BC different from the curve AB so as to reach a point C. Furthermore, applying the drive voltage in the negative direction causes the amount of polarization to reach a point D at a minimum drive voltage (xe2x88x92VDMAX), and returning the drive voltage VD again to 0 causes the amount of polarization to return to the original point A.
Consequently, depending on the hysteresis of the applied voltage, the ferroelectric capacitor can take different amounts of polarization like the point A or the point B even with no voltage applied. In this case, assuming the state of point A as a logical xe2x80x9c1xe2x80x9d and the state of point C as a logical xe2x80x9c0xe2x80x9d makes it possible to hold two values in a state that the applied voltage is zero.
That is, this ferroelectric memory fulfills a nonvolatile memory that needs no refresh operations or a low power consumption memory that requires fewer refresh operations than DRAMs by using the above hysteretic property. Whereas write operation on the ferroelectric memory is performed by applying a drive voltage to the electrodes of the ferroelectric capacitor as described above, read operation thereon is done similarly by applying a voltage to the ferroelectric capacitor.
In this connection, in conventional 1T1C type ferroelectric memories, a bit line and a drive line to which the ferroelectric capacitor is connected via the selector transistor are controlled prior to a read operation so as to be equal in potential to each other, so that the bit line is already in a floating state at the time of the read operation. In this case, given a capacitance Cf of the ferroelectric capacitor and a wiring capacitance Cb of the bit line, the resultant equivalent circuit is as shown in FIG. 8.
Then, when the drive voltage VD is applied to a drive line DL, a relational expression of a voltage Vb of a bit line BL can be expressed as follows, where the amount of charges stored in the ferroelectric capacitor is assumed to be Q:
Q=Cf(VDxe2x88x92Vb)=CfVf 
Q=CbVb 
where Cf is the nonlinear capacitance inherent in the ferroelectric and Vf is the voltage actually applied to the ferroelectric capacitor.
From these equations, it can be understood that with respect to the voltage Vb outputted to the bit line BL, actual Q and Vb can be determined from an intersecting point between a hysteresis graph of the performance chart showing Q-V characteristics of the ferroelectric capacitor and a load line passing through a point (V,Q)=(VD,0) with a gradient of xe2x88x92Cb.
Accordingly, in a state that a logical xe2x80x9c1xe2x80x9d has been written, turning ON the switch (selector transistor) so that VD goes xe2x80x9cHxe2x80x9d results in performance line and load line transitions as shown in FIG. 9, showing that an actual result of (Vf,Vb,Q)=(Vf1,Vb1,Q1) can be determined from an intersecting point A1. Likewise, in a state that a logical xe2x80x9c0xe2x80x9d has been written, turning ON the switch (selector transistor) so that VD goes xe2x80x9cHxe2x80x9d results in transitions as shown in FIG. 10, allowing (Vf,Vb,Q)=(Vf0,Vb0,Q0) to be determined from charge amount and voltage at an intersecting point A0. In this connection, since the voltage Vb1 and the voltage Vb0 take different values from each other, enough voltage difference therebetween allows data read by a sense amplifier SA or the like to be achieved.
On the other hand, in the 2T2C type ferroelectric memory, spontaneous polarizations in different directions have been written in a set of two ferroelectric capacitors, respectively, and inverted or noninverted charges of amounts resulting from driving the individual ferroelectric capacitors are outputted to a bit line and a bit line bar, where levels of those voltages are compared with each other for achievement of data read. For this purpose, the 2T2C type ferroelectric memory has a margin about double that of the 1T1C type ferroelectric memory.
Next, the second mode employs ferroelectric thin film instead of gate oxide of the gate transistor, being also called MFS-FET (Metal/Ferroelectric/Semiconductorxe2x80x94Field Emission Transistor) or 1-transistor (1T) type ferroelectric memory. In this second mode, data storage and read are enabled by determining whether to turn ON or OFF the transistors by using carriers induced to the semiconductor by spontaneous polarizations of the ferroelectrics.
In the case of the 1T type ferroelectric memory, since read is carried out in a static state, nondestructive read is enabled.
However, these 1T1C type ferroelectric memory and 2T2C type ferroelectric memory as the first mode of the prior art have a problem as shown below. That is, the 1T1C type ferroelectric memory and the 2T2C type ferroelectric memory are of the method that involves outputting a remanent polarization amount of the ferroelectric capacitor to a bit line and reading the level of a voltage outputted to the bit line.
With data of xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d stored in the ferroelectric capacitor, if the amount of charges to be outputted to the bit line by a read operation is Qf1 or Qf0 and if the capacitance of the bit line is Cb, then the voltage Vb1 or Vb0 induced to the bit line can be expressed as follows:
Vb1=Qf1/Cb 
Vb0=Qf0/Cb. 
Therefore, read margin xcex94V can be expressed as
xcex94V=Vb1xe2x88x92Vb0. 
In this case, along with scale-down, capacitor area of the ferroelectric decreases in proportion to F2, where a minimum machining size is assumed to be F. Therefore, whereas the output charge amount Qf also decreases in proportion to F2, the bit line capacitance Cb scarcely decreases. Accordingly, as the memory cells are reduced in scale, the hysteresis graph of the performance chart shown in FIG. 9 results in one indicated by dotted line. This results in a problem that the bit line voltage for a logical xe2x80x9c1xe2x80x9d decreases as shown by Vb1xe2x80x2, so that the read margin xcex94V decreases resultantly, making data read hard to achieve, unfortunately.
In this case, decreasing the number of ferroelectric capacitors connected to one bit line BL makes the wiring capacitance Cb of the bit line BL decreased (making the gradient of the load line gentler), thus making the bit line voltage Vb1xe2x80x2 increased, with the read margin xcex94V increased. However, in this case, keeping the total number of ferroelectric capacitors of the semiconductor storage device unchanged would cause the number of bit lines BL to increase, making the number of sense amplifiers increased as well proportionally. Accordingly, due to the increase in the number of sense amplifiers, the area of the semiconductor storage device also increases, posing a problem that integration cannot be attained for the reduction in the memory cells while the cost is increased.
Meanwhile, the 1T type ferroelectric memory as the second mode of the prior art has the following problems. That is, for the 1T type ferroelectric memory, indeed such problems associated with scaling as described above do not occur, but because of the need for forming a ferroelectric, which is an oxide, directly on oxidation-prone silicon, it is very difficult to obtain successful interfaces. That is, upon occurrence of a SiO2 layer even to a few nm due to oxidation of silicon, because of SiO2xe2x80x2s quite low dielectric constant compared with ferroelectrics, most of the voltage applied to the gate electrode would be applied to the SiO2 layer, so that the direction of polarization of the ferroelectric could not be inverted without applying a stronger voltage. This poses a problem that the operating voltage would be higher resultantly.
Also, as a solution to the above issue in manufacture, there has been proposed a 1T type ferroelectric memory called MFIS-FET in which not the ferroelectric is deposited directly on the silicon substrate, but a paraelectric buffer layer is interposed therebetween or a 1T type ferroelectric memory called MFMIS-FET in which a conductor is formed on a buffer layer. Even in these cases, however, the ferroelectric memories are difficult to manufacture and moreover the voltage would be applied even to the buffer layer, leading to a problem that the voltage to be applied to the ferroelectric would be decreased resultantly.
Furthermore, in the case of the MFMIS-FET, charges stored in the conductor in a write operation causes a potential difference to be generated between the conductor and the gate, leading to occurrence of leaks. This poses a problem that stable data retention for prolonged time would be difficult to achieve.
Accordingly, an object of the present invention is to provide a semiconductor storage device which is highly integratable and high in reliability and which is capable of power consumption reduction and high-speed operation and further which employs an easy-to-fabricate ferroelectric thin film.
In order to achieve the above object, according to the present invention, there is provided a semiconductor storage device comprising:
a memory cell which includes a ferroelectric capacitor and a selector transistor, the ferroelectric capacitor comprising a first electrode, a second electrode opposed to the first electrode, and a ferroelectric thin film sandwiched between the first electrode and the second electrode, and the selector transistor having a first main electrode connected to the second electrode;
a drive line connected to either one of the first electrode of the ferroelectric capacitor or a second main electrode of the selector transistor;
a bit line connected to the other one of the first electrode of the ferroelectric capacitor or the second main electrode of the selector transistor; and
a read transistor having a gate electrode connected to the bit line.
With this constitution, for a read operation, the bit line and the drive line are pre-charged so as to become equal in potential to each other. After that, the bit line is set floating, the selector transistor is turned ON, and the drive line is boosted up to a drive voltage. In this operation, if the voltage difference of the bit line between inverted and noninverted modes is sufficiently larger than the threshold voltage of the read transistor, then the read transistor is automatically turned ON in the case of inversion, so that an output for read can be obtained.
As shown above, voltages of the bit line in the inverted mode and noninverted mode are discriminated by the read transistor. Therefore, when the number of memory cells connected to the bit line is reduced in order to lower the wiring capacitance of the bit line, then the number of bit lines would increase, given that the total number of memory cells is maintained unchanged, where the number of read transistors would also increase proportionally. Nonetheless, increases in area and cost due to the increase in the number of read transistors do not matter, compared with the case where the sense amplifier is used as in the prior art.
From the above description, the voltage induced to the bit line can be regarded as not depending on the absolute quantity of remanent polarization of the ferroelectric capacitor. Accordingly, it becomes implementable to reduce the capacitor area of the ferroelectric capacitor and to fulfill a high-integration semiconductor storage device.
Also, in an embodiment, at least two of the memory cells are connected in parallel to the bit line, and one main electrode of a block-selector transistor is connected to one end of the bit line, thereby constituting a memory cell block;
the bit lines of at least two of the memory cell blocks are connected in series via the block-selector transistor.
If the number of memory cells connected in parallel to the bit line is increased, the stray capacitance (wiring capacitance) of the bit line also increases. As a result, as can be seen from FIG. 9, the output voltage Vb1 to the bit line particularly in the inversion mode would be lowered, causing the read margin to be decreased. In this embodiment, the memory cell block includes the bit line in which at least two memory cells are connected in parallel, and the bit lines of at least two memory cell blocks are connected in series via the block-selector transistors. Thus, by setting the number of memory cells connected to the bit lines of the memory cell blocks so that the stray capacitance (wiring capacitance) of the bit lines comes to allow an optimum read margin to be obtained, both enhanced multiple memory cells and optimum read margin can be fulfilled at the same time. Moreover, the semiconductor storage device becomes accessible without using a sense amplifier, thus capable of high-speed operation.
Also, in an embodiment, the bit line and the drive line are disposed in parallel to each other.
In this embodiment, the bit lines and the drive lines, which are connected to both ends of the memory cell, are disposed parallel to each other. Accordingly, the word line connected to the gate electrode of the selector transistor and the drive line cross each other perpendicularly. As a result, through the selection by the word line and the application of the drive voltage by the drive lines, only one memory cell located at the cross-point of the word line and the drive line is accessed Thus, reduction in power consumption and high speed operation are enabled. Moreover, as a result of this, the number of read/rewrite operations is reduced to a large extent, so that the semiconductor storage device can maintain high reliability.
Also, in an embodiment, the bit line and the drive line are disposed vertical to each other.
In this embodiment, the bit line and the drive line connected to both ends of the memory cell are disposed vertical to each other. Accordingly, the word line and the drive line connected to the gate electrode of the selector transistor are parallel to each other. As a result, through the selection by the word lines and the application of the drive voltage by the drive lines, all the memory cells that are connected in parallel to the word lines and the drive lines are accessed. Thus, 1-line batch operation is enabled.
Also, in an embodiment, electric capacitance of the bit line is not less than xc2xd and not more than five times electric capacitance of the ferroelectric capacitor that does not include any inverted charge amount.
In this embodiment, the hysteresis curve can intersect the load line representing the bit line capacitance Cb in the inversion region of the performance chart of the ferroelectric capacitor in the inversion mode. Therefore, the voltage difference of the bit line between inversion and non-inversion can be obtained as not less than a specified value stably, allowing a large read margin to be obtained.
Furthermore, only a voltage around the anti-voltage is applied to the ferroelectric capacitor during the read operation in the inversion mode, hence not a perfect inversion. Thus, such deteriorations as fatigue or so-called imprints of the ferroelectric memory hardly occur, so that the semiconductor storage device can maintain high reliability.
Also, in an embodiment, anti-voltage of the ferroelectric capacitor is not less than {fraction (1/10)} and not more than xc2xd of its drive voltage.
In this embodiment, the anti-voltage of the ferroelectric capacitor is not more than xc2xd of the drive voltage. Accordingly, the output voltage to the bit line is increased in the inversion mode. Further, the anti-voltage of the ferroelectric capacitor is not less than {fraction (1/10)} of the drive voltage. Accordingly, it never occurs that excessively small anti-voltage causes the electric capacitance in the non-inversion mode to increase, and therefore the output voltage to the bit line is decreased. As a result, the voltage difference of the bit line between inversion and non-inversion can be obtained as not less than a specified value stably, allowing a large read margin to be obtained.